An architecture for intermediate area-time complexity multiplier

The area and time of traditional array and Wallace tree multipliers depend on operand bit-size. An intermediate multiplier which has higher speed but occupies more area than a traditional array multiplier is proposed. When compared with a traditional Wallace multiplier, it has lower speed and area. The authors' multiplier resembles an array multiplier in terms of regularity in placement and interconnection of unit computation cells. In contrast to a traditional array multiplier, it computes by introducing multiple computation wave fronts in its partial product core.<>