A systematic methodology for designing multilevel systolic architectures

A systematic graph-based methodology for designing systolic arrays that can perform concurrently is introduced. Partitioning an iterative algorithm into subalgorithms, the authors describe each of them, as well as their interdependences, with a set of uniform recurrent equations. Alternative architectures can be designed by mapping the dependence graph of the algorithm onto hardware. The main feature of the proposed architectures is the significant reduction of the computation time of an algorithm.<>