Double edge triggered devices: Speed and power constraints

A new set of double edge triggered flip-flops has been developed. It requires fewer transistors to implement than earlier designs. The energy consumption in the authors' double edge triggered flip-flops is shown to be lower than in single edge triggered (SET) flip-flops. This is demonstrated by architecture level analysis, circuit analysis and simulation techniques. The maximum data rate in double and single edge triggered flip-flops is also compared via simulation.<>