Clock distribution design in VLSI circuits-An overview

Clock distribution networks synchronize the flow of data signals between data paths, and the design of these networks can dramatically affect system wide performance and reliability. The field of clock distribution design can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom VLSI systems; 2) the automated synthesis of clock distribution networks with application to automated synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells, and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the specification of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described and summarized. Future trends are discussed.<>