Thermal failure simulation for electrical overstress in semiconductor devices

Electrical overstress (EOS) and electrostatic discharge (ESD) constitute one of the most dominant threats to integrated circuits (ICs). A nonlinear 2-D/1-D thermal simulator suitable for ESD/EOS thermal failure modeling in ICs is reported. The unboundedness of the thermal problem is addressed by a special set of boundary conditions, making the thermal simulation task computationally efficient. Simulated power-to-failure vs. time-to-failure relationships (power profiles) for various combinations of major IC structural parameters are presented and compared with experimental data.<>