Short-circuit power dissipation formulae for CMOS gates

Short-circuit power dissipation contributes significantly to the overall power dissipation in integrated circuits. A new formula is developed for the estimation of short-circuit power dissipation in CMOS logic gates based on /spl alpha/-power law model that includes velocity saturation effects of short-channel MOSFETs. A technique is developed for the measurement of short-circuit current and power dissipation of CMOS logic gates for use in circuit simulation. SPICE (simulation program with IC emphasis) simulation results are used to determine the accuracy of the new formula.<>