An efficient 175 MHz programmable FIR digital filter

An efficient 175-MHz programmable finite impulse response (FIR) digital filter is implemented. It uses a novel switchable unit-delay to allocate the optimal hardware resources to each filter tap. The authors' prototype circuit can have up to 32 linear taps with 16-bit I/O in a die size of 5.9mm by 3.4mm using 1.2 /spl mu/m CMOS technology. A simple recoding of the coefficient values results in a simplification of the digit multiplication hardware. On-chip testing circuitry permits the testing of the chip at a high frequency.<>