Video DSP architecture for MPEG2 codec | IEEE Conference Publication | IEEE Xplore

Video DSP architecture for MPEG2 codec


Abstract:

We developed a DSP named VDSP2 (Video Digital Signal Processor version 2) for MPEG2 video coding and decoding. In order to obtain the necessary performance, we employed a...Show More

Abstract:

We developed a DSP named VDSP2 (Video Digital Signal Processor version 2) for MPEG2 video coding and decoding. In order to obtain the necessary performance, we employed a 2-level parallel processing scheme consisting of a pipeline processing at the macro block level and a parallel vector processing using a SIMD configuration at the block level. In the VDSP2, we included a DSP core which execute 4 parallel vector operations and scalar operations, a DRAM controller, a DCT/IDCT circuit, a VLC/VLD circuit including a programmable controller and a data communication circuit. As a result, the real-time encoder specified in MPEG2 can be realized with two VDSP2 chips, and the decoder can be realized with one VDSP2 chip.<>
Date of Conference: 19-22 April 1994
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-1775-0
Print ISSN: 1520-6149
Conference Location: Adelaide, SA, Australia

References

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