A symmetric Vss cross-under bitcell technology for 64 Mb SRAMs

A 0.25 /spl mu/m CMOS technology designed for a new symmetric Vss Cross-Under (XUnder) bitcell has been developed for a 64 Mb SRAM. The new symmetric bitcell is based on a simple geometry of orthogonal active and gate poly features which minimizes the height/width aspect ratio of the bitcell, resulting in a wider column decoder pitch. A new inverted spacer TFT has been adopted as the load element in the bitcell. Bitcell features fabricated using X-ray lithography demonstrate that a simple NCL isolation approach can be used to define 0.625 /spl mu/m active pitch features without evidence of oxide punchthrough thus alleviating the need for more aggressive approaches such as shallow trench isolation.<>