Simulation model for analysis of synchronous digital hierarchy network payload jitter

Since pointer processing in SONET/SDH networks is a complex non-linear process, computer simulation is required to accurately characterize the network jitter induced in the underlying PDH payloads. While previous behavioral network models provide accurate results for normal synchronous operation, they do not model the periodic pointer sequences which occur during holdover mode. This paper's methodology uses a more detailed event-driven simulator which models an SDH network at a bit-by-bit level. These bit-by-bit simulation results are used in conjunction with an ITU specified jitter measurement filter to generate accurate jitter waveforms for SDH holdover mode operation. This methodology allows detailed analysis of the jitter caused by both payload mapping definitions and network pointer processor implementations. Hence, this methodology may be used to evaluate network jitter reduction algorithms.<>