Cellular neural network chips with optical image acquisition

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capability. Pixel smartness is achieved by exploiting the cellular neural network paradigm, incorporating at each Spixel an analog computing cell which interacts with those of nearby Spixels. The authors propose a current-mode technique for CNN-Spixel chips and give measurements from two 16/spl times/16 prototypes in a single-poly double-metal CMOS n-well 1.6 /spl mu/m technology. One of these prototypes is designed for the application of connected component detection (CCDet), and the other to calculate the radon transform (RT) of an input image. The CCDet chip obtains a density of /spl sim/89 Spixels (sensory+regulation+processing) per mm/sup 2/, with a power consumption of 105 /spl mu/W per Spixel. The sensory+regulation circuitry amount to /spl sim/30% of the total Spixel pixel area and the rest corresponds to the processing circuitry. Area and power figures for the RT chip are similar. These area and power figures, and the fact that connections among pixels are made by abutment (requiring no extra routing area) enable forecasting single-die CMOS chips with 100/spl times/100 complexity and about 1 W power consumption.<>