Synergy of synthesis and test (logic design)

An integrated, compiler-driven approach to digital chip design that automates scan-based design and test pattern generation for 100% stuck at fault coverage is presented. The design process was partitioned into four major steps: compiler-driven unified structural/functional specification; logic synthesis that maps Boolean specifications into a net list of standard cells, scan-based test pattern generation; and fully automated standard cell layout. It has been shown that routine application of high-level design specification and logic synthesis can significantly reduce the problem of test pattern generation. The approach is especially well suited for designs where reducing design time is more important than minimizing silicon area. The components of the modular testability system are discussed with emphasis on hierarchical test pattern generation and redundancy removal techniques.<>