Delayed consistency and its effects on the interconnection network of shared memory multiprocessors

In large-scale shared-memory multiprocessors, the delayed consistency memory models are efficient for tolerating the large latency of the processor-memory interconnection network. In the delayed consistency memory models most of the write requests do not block the processor whereas the read requests do, so the read requests are more urgent than the write requests are. If an urgent read request is blocked by less urgent write requests in the processor-memory interconnection network, priority inversion arises because the read request should have a higher priority than the write requests. We show the priority inversion effects on the performance of the shared-memory multiprocessors, and demonstrate how much the performance can be improved by removing the priority inversion. With a performance analysis based on simulations, we could observe that removing the priority inversion speeds up the execution of parallel programs especially when the bandwidth of the interconnection network is small and the cache miss rate of a parallel program is high.<>