Induced end-of-life errors in a fast settling PLL

The authors present a mathematical description of the second-order type II PLL (phase-locked loop), which may deviate from ideal when undesired inputs, commonly arising in hardware, are incurred by the system. Satisfactory EOL (end-of-life) performance is guaranteed when such transients are accounted for. The authors present a methodology for predicting expected EOL LSE excursions and demonstrate the system's dependence on this parameter. A PSpice model and empirical data from a 5-GHz spaceborne PLL verify acceptable degradation at EOL when an EOL transient is present.<>