Performance of the 3-D sidewall flash EPROM cell

We report on the performance of a promising new 3-D sidewall flash EPROM cell that has been implemented in a novel memory array. The 3-D flash EPROM is a vertical stacked gate cell with both floating and control gates surrounding a silicon pillar. The cell size is within 10% of the square of the minimum pitch and can be scaled without encountering punchthrough or isolation constraints. The cell has fast write and erase speeds and is suitable for 5V only operation. Read current is 3/spl times/ that of an equivalent generation conventional NOR-type cell.<
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