High-performance CMOS with oxidation-planarized twin tubs and one-mask sealed diffusion-junctions

Issues of submicron integration in vertical topography, junction silicide, and contact integrity are summarized. Examples include (1) high cost of twin-tub formation to achieve planarity at tub boundaries, (2) silicide-related nonuniformity or defects on shallow junctions, and (3) coverage of a TiN diffusion barrier layer at bottom corners of contact windows. We present a simple process to attack the issues. The process requires only ten masks for a full-CMOS integration with two-level metallization. It also improves the integration density and circuit performance.<>