A physical poly-silicon thin film transistor model for circuit simulations

This paper presents a poly-silicon thin film transistor model for circuit simulations. The drain current model includes the effects of hot carriers, drain induced barrier lowering (DIBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is weakly linked to the drain current and its derivatives. This model has been implemented in a SPICE simulation and experimental results are compared.<>