A 300 MIPS, 300 MFLOPS four-issue CMOS superscalar microprocessor

A RISC CMOS superscalar microprocessor, operating at 75 MHz, executes up to four instructions per clock cycle, totalling 300M instructions per second. The chip implements a 64 b architecture and includes a 64 b integer pipeline, 16 kB instruction cache (Icache), 16 kB data cache (Dcache), 1 k entries of branch cache (Bcache) for branch prediction and a 384 entry translation lookaside buffer (TLB). The chip has a separate floating-point unit (FPU) with maximum performance of 300MFLOPS. The FPU is fed by two 64 b-wide banks of external cache configurable from one to 16 MB. The chip set has a mechanism for treating 32 b operation as a subset of the 64 b architecture and supports multi-processing. The chip is fabricated in 0.5 /spl mu/m CMOS with triple layer metal, double poly Si for high density cache and triple-well. The die is 17.34/spl times/17.30 mm/sup 2/ and includes 2.6 M transistors. The package is a 59 1-pin CPGA with 382 signal pins. Power dissipation is 13 W from a 3.3 V supply at 75 MHz.<>