A hardware cache coherency scheme for multiprocessors

In this paper, we discuss a hardware cache coherency scheme for shared memory multiprocessors. The scheme consists of a cache coherency protocol and a hardware scheme for cache coherency. Use of the scheme allows one to split cache coherency operations between the participating processors. Protocol states and operations are discussed. A cache controller architecture is proposed for this protocol and its design details are discussed. Performance of the coherency scheme is also discussed.<>