Partitioned and parallel cyclic redundancy checking

In this paper, the linear feedback shift register (LFSR) is redesigned to process several bits of a long data stream simultaneously in order to obtain a signature more quickly. The resulting structure is capable of encoding, decoding, detecting, and correcting errors in cyclic codes partitioned into variable length words; hence, it is given the name partitioned parallel encoder, decoder, detector, corrector (pPEDDC). A simple pPEDDC VLSI chip has been fabricated and used to extract performance measures for comparison with equivalent LFSR implementations.<>