A parallel CMOS 2's complement multiplier based on 5:3 counter

A parallel 8/spl times/8 2's complement multiplier based on a novel 5:3 counter is presented. The structure of the multiplier is simple, regular, and very suitable for VLSI implementation. Compared with Wallace tree and Redundant Binary Addition Tree (N. Takagi et al., 1985), the proposed scheme requires less levels for the same number of partial products, resulting in a simpler and faster circuit.<>