High voltage pullup devices in a BiMOS HVIC technology

High-voltage complementary pullup and pulldown devices have been fabricated in a high-voltage integrated circuit process that is based on thin epitaxial layers (<10 mu m). The device structures described allow high-voltage pullup devices to be realized where normally only pulldown devices would be possible in such thin epitaxial layers. Only one additional mask was needed to incorporate these devices into the existing junction-isolated BiMOS technology. A 400-V chip featuring in high-voltage, low-power consumption drivers along with 5-V CMOS logic has been fabricated using novel depletion-mode NMOS design.<>