Novel InP/InGaAs double-heterojunction bipolar transistors suitable for high-speed IC's and OEIC's

This paper proposes a novel collector structure for high-performance InP/InGaAs double-heterojunction bipolar transistors (DHBT's) with layer compatibility for high-speed pin photodiodes (PD's) and describes their successful performance. The collector has a potential notch formed by thin p/sup +/- and n/sup +/-InGaAs layers between a relatively thick undoped InGaAs layer and an N-InP layer. The notch effectively suppresses the electron blocking effect, which is generally observed in DHBTs at high collector current. The thin p/sup +/-InGaAs layer also raises the conduction band in the collector to enhance the ballistic transport of electrons. Breakdown voltage increases because the major part of the potential change at high collector bias occur in the N-InP layer due to the spreading of the depletion layer. The layer compatibility of both the high-performance DHBT's and high-speed PD's enables us to easily manufacture optoelectronic integrated circuits (OEIC's), because of the simultaneous layer growth and device fabrication of PD's and DHBT's without any additional process. We obtained 160-GHz f/sub T/ and 162-GHz f/sub max/ for a DHBT with a 1.6/spl times/4.6-/spl mu/m/sup 2/ emitter. The f/sub T/ value reached 124 GHz at low V/sub CE/ of 0.65 V owing to the suppressed electron blocking effect. A small DHBT with a 0.6/spl times/1.6-/spl mu/m/sup 2/ emitter operated with 118-GHz f/sub T/ and 148-GHz -f/sub max/ at an I/sub c/ as low as 1 mA. A photoreceiver OEIC comprising a pin PD and an HBT preamplifier operates error free up to 6 Gbit/s for 1.55-/spl mu/m wavelength NRZ signals.<>