Modeling of broken connections faults in CMOS ICs

This work presents a fault model to effectively account for broken connections inside CMOS circuits. The proposed model is very general, since it allows one to detect broken connections that cannot be individualized by means of test sequences for stuck-open faults; in addition, the detection of a broken connection in a node ensures the detection of all stuck-open faults of the transistors connected to that node. Conditions for the detection of broken connections are derived from electrical considerations and the minimum number of input vectors to be applied to test for a broken connection in a node is determined by graph theory. The model can be used to derive tests and to perform fault simulations independently of the actual layout of the circuit.<>