Dual (n/sup +p/sup +/) polycide gate technology using Si-rich WSi/sub x/ to exterminate lateral dopant diffusion

We have developed a new technology to solve the device degradation of the dual-polycide-gate N/sup +P/sup +/ CMOS due to the lateral dopant diffusion in the silicide. This was realized by using a Si-rich WSi/sub x/ without any other process steps. With this technology, no significant threshold voltage shift was observed in PMOS even after 900/spl deg/C annealing. This is because the grain growth of the excess Si in the WSi/sub x/ blocks the lateral dopant diffusion path.<>