Circuit partitioning for multiprocessor SPICE

Circuit partitioning issues for circuit simulation on distributed multiprocessors are discussed in this paper. An efficient three level partitioning algorithm for large-scale circuit is proposed. Using this algorithm, we can partition a large-scale circuit into r sub-circuits of similar size while keeping the interconnect set to a minimum. This algorithm may also be implemented in parallel. An example is provided to show the performance of the algorithm.<>