Resolving horizontal constraints and minimizing net wire length for multi-layer channel routing

The channel routing problem in VLSI design is to route a specified interconnection among modules in as small an area as possible. Hashimoto and Stevens (1971) proposed an algorithm for solving the two-layer channel routing problem in the absence of vertical constraints. In this paper, we analyze this algorithm in two different ways. In the first analysis, we show that a graph-theoretic realization, algorithm MCC1, runs in O(m + n + e) time, where m is the size of the channel specification of n nets, and e is the size of the complement of the horizontal constraint graph. In the second analysis, algorithm MCC2, we show that a time complexity of O(m + n log n) can be achieved. Algorithms MCC1 and MCC2 guarantee optimum routing solutions under the multi-layer V/sub i+1/H/sub i/ (i/spl ges/1) routing model, where the horizontal and vertical layers of interconnect alternate. Finally, we consider the problem of minimizing the total net wire length in the V/sub i+1/H/sub i/ (i/spl ges/1) routing model. Given a channel specification and a partition of the set of nets (where the nets within each part of the partition are non-overlapping), we propose an O(m + d/sub max/log d/sub max/) time algorithm for minimizing the total net wire length, subject to the condition that nets from a part of the partition are assigned to the same track. All our solutions use the minimum number of via holes.<>