On implementing large fault-tolerant binary tree architecture in WSI

A new layout scheme for fault-tolerant binary tree architecture in WSI with a high area utilization, short propagation delay, and short edge length is proposed. In the new layout scheme, the binary tree is partitioned into fault-tolerant modules. Each module can contain 3 active processors and k spares. That is, each fault-tolerant module can be connected to 4 other fault-tolerant modules. The new scheme can also be used to provide area efficient layout for previously proposed fault-tolerant binary tree architectures.<>