An experimental investigation of EEPROM reliability issues using the progressional offset technique

A set of novel EEPROM test structures have been designed and fabricated, in which gate/drain overlap is incremented in a number of well defined steps. These have been used to emulate EEPROM programming conditions, and measure endurance. The structures have enabled EEPROM endurance to be investigated as a function of drain doping species (As and P), for a spectrum of floating gate/drain overlaps.<>