Performance-oriented architecture design/re-design methodology

The authors propose a performance-oriented design/re-design methodology for pipelined computer architectures using heuristic logic modification. The hardware data flow of the CPU (Central Processing Unit) can be modeled as a network. However, no mathematical formalizations and analyses of this network are available, because usually many entities of the network are tightly connected and often form loops. The proposed method executes a performance simulation, identifies the bottleneck or entity to be improved, and modifies the network with use of modification rules. This method is effective for both first time architecture design and architecture re-design, the design of another CPU with the same software-hardware interface.<>