A micro-pipelined zero suppression, trigger matching and recalibration integrated circuit

A pipelined integrated circuit architecture performing data extraction and buffering functions in order to reduce the volume of data from the front-end electronics is presented. This architecture performs data reduction as early as possible in order to reduce the buffering needed for the latency of the first level trigger decision. Three different ways of reducing data are provided: selective zero suppression, synchronisation with the first level trigger and suppression of unaccepted events, and feature extraction. After extracting the required information from the raw data samples, data are organized into packets which can be injected into an event-building packet switching network. Elastic buffers between the functional units enable them to work independently and asynchronously. This removes the strict system-wide timing requirement between the input samples, the first level trigger, and the read-out. An evaluation chip containing basic building blocks of the architecture has been built using micro-pipelining and self-timed asynchronous circuitry. This design style offers reduced power consumption, low noise, and very high speed. Implemented in a full-custom 1.2 mu m CMOS technology, it was measured to run internally at 140 MHz.<>