An analytical quasi-saturation model considering heat flow for a DMOS device

This paper reports an analytical quasi-saturation model considering heat flow for a DMOS device. As verified by the PISCES results, the analytical model, which considers heat flow provides a good prediction of the much worse quasi-saturation behavior due to the elevated lattice temperature. This is a result of the limited heat sinking capability of the thermal contact node. Based on the analysis, for a DMOS device operating with a contact thermal resistance of less than 10/sup 4/ K/W, the drain current at quasi-saturation is found acceptable with a lattice temperature below 350 K.<
>