32-bit PI-bus versus 32-bit Futurebus+ performance comparison

This paper presents a performance analysis of the JIAWG 32-bit Parallel Intermodule (PI) Bus versus a 32-bit Futurebus+ Standard backplane bus. Performance was measured in terms of bus throughput and latency, using a test scenario representative of a real-time, avionics application. The test scenario communications mix was constructed using Rate Monotonic Scheduling (RMS) theory. Behavioral VHDL models of both buses were used to execute the test scenario in a VHDL simulation environment. Simulation results were used to test whether critical deadlines were met for a given bus utilization (throughput) level. PI-Bus performance using the datagram, short-header, non-acknowledged format was compared to Futurebus+ performance using compelled mode, both with and without the message-passing protocol defined in IEEE Futurebus+ 896.1.<>