Basic building blocks for asynchronous packet routers

Propagating the clock through large networks and providing correct functioning of the system is a serious engineering problem. The clock appears at different moments for two different physical points/spl minus/clock skew problem. While the clock skew can be neglected for small systems, it results in major problems when building large concurrent networks. To overcome such problems the authors believe that the absolute solution is to eliminate the notion of clocking entirely throughout by adopting asynchronous design techniques. Packet switches are familiar components of concurrent architectures and a good example to illustrate asynchronous design. The paper describes the asynchronous implementation of three basic building blocks for asynchronous packet routers and also demonstrates asynchronous design techniques for VLSI design.<>