Reducing the probability of common-mode failure in the fault tolerant parallel processor

The Fault Tolerant Parallel Processor (FTPP) has been designed in strict accordance with the theory of Byzantine Resilience and meets all the known requirements for tolerating arbitrary random hardware faults. We have broadened our scope to provide very high coverage for common mode faults (CMFs). A layered defense approach against CMFs has been developed that consists of fault avoidance, fault removal and real-time fault tolerance that can be applied during the requirements specification, design and development phases test and validation phases and operational phases, respectively. This paper provides a taxonomy of common-mode faults and describes the layered defense approach against CMF being used in the FTPP.<>