Bias temperature reliability of n/sup +/ and p/sup +/ polysilicon gated NMOSFETs and PMOSFETs

A comparison of bias temperature reliability for submicron p/sup +/ and n/sup +/ polysilicon gated devices is presented. An instability associated with the p/sup +/ polysilicon gated devices that gives a negative Delta V/sub t/ and an interface-state buildup for positive bias temperature (+BT) was observed. This instability is explained in terms of the amount of the hydrogen-bonded component of moisture that remains in the gate electrode. It is further shown that a proper postmetallization anneal will significantly reduce this instability. Therefore, it is concluded that high BT reliability for p/sup +/ polysilicon gated devices can be achieved with process controls and actions that reduce the moisture in the device-active area. These controls provide an adequate reliability margin in dual work-function designs.<>