A 16 b low-power-consumption digital signal processor

A 16-b digital signal processor (DSP) is described that realizes an 11.2-kb/s vector sum-excited linear predictive (VSELP) speech codec, chosen as the digital cellular standard in Japan. Power consumption of 70-mW at 3.5-V VDD is achieved by using a double-speed multiply-accumulate system, by improving logical and transistor circuits, and by using a 0.8- mu m double-metal-layer CMOS process and a low-VDD supply. The block diagram of this DSP is shown along with the mechanism of double-speed MAC operation.<>