Effects of transistor reordering on the performance of MOS digital circuits

The effect of transistor reordering on the tuning behavior of MOS circuits is investigated. The investigation is performed by analyzing the transient response of series connected MOS structures (SCMSs) using SPICE. The investigation shows that the effect of transistor reordering on the timing performance of a MOS logic gate varies significantly depending on transistor strengths, stack height, load capacitance and critical input signal transition time. Circuits for which the effect of transistor reordering on timing is insignificant are clearly identified.<>