Optimization of digital BiCMOS circuits, an overview

An overview of the optimization of buffer chains and multilevel logic in a BiCMOS environment, including scaling effects, is presented. The BiCMOS speed-up contours are reviewed. The use of these contours and analytical delay expressions in the design and optimization of BiCMOS buffer chains is also reviewed. The performance differences between different types of multi-stage mixed CMOS/BiCMOS buffers are summarized. Different BiCMOS current-mode logic (CML) circuits, such as the multi-emitter BiCMOS CML circuits, are considered. The performance advantages of using such circuits in implementing multilevel logic are summarized.<>