CMOS cells for analog VLSI Laplace equation solver based on the resistive analogy method

An analog VLSI Laplace equation solver is described. The system uses MOS transistors in ohmic mode to simulate a resistive grid of cells similar to the resistive analogy method used for solving the Laplace equation. The VLSI circuit is a two-dimensional array of cells, each of which can be configured digitally to simulate a resistive or a boundary cell. The CMOS cell implementation and the overall system architecture are discussed.<>