Design of a 32-bit fully asynchronous microprocessor (FAM)

The authors describe a 32-b fully asynchronous microprocessor (FAM) with the four-stage pipeline based on a reduced instruction set computing (RISC)-like architecture. Issues relevant to the processor such as design of the self-timed data path, the asynchronous controller and interconnection circuits are discussed. The FAM showed an average operation speed of 3.5 ns for each instruction on 0.5- mu m CMOS technology. Simulation results are included using parameters extracted from the layout.<>