The Post Office experience: Designing a large asynchronous chip

The Post Office is an asynchronous, 300000 transistor, full-custom CMOS chip designed as the communication component for the Mayfly scalable parallel processor. Performance requirements led to the development of a design style which permits the design of sequential circuits operating under a restricted form of multiple input change signaling called burst-mode. The Post Office complexity forced the authors to develop a set of design tools capable of correctly synthesizing transistor circuits from state machine and equation specifications, and capable of verifying the correctness of the resultant circuitry using implementation specific timing assumptions. A case study of this design experience is provided.<>