Pipeline banyan-a parallel fast packet switch architecture

The authors propose a new fast packet switch architecture. This switch has a control plane and a number of parallel data planes which are of the same banyan topology. Packet headers are routed via the control plane to set the corresponding routing paths in the data planes. Since the data planes do not need to do routing decisions, their hardware complexity can be reduced. The pipeline banyan has output queuing capability and can approach 100% maximum throughput. It can deliver packets in a sequential order. The internal switching speed needs only to be a fraction of the input port speed. The basic structure is a regular N*N banyan which is suitable for VLSI implementation.<>