VLSI architectures for the full-search blockmatching algorithm

Systolic VLSI architectures for an implementation of the full-search block-matching algorithm are described. A large range of data rates can be efficiently covered by the proposed architectures. The input bandwidth problem for the search-area data is solved with on-chip line buffers. Two data input modes are investigated: line-scan mode and block-scan mode. A VLSI realization with a very low transistor count and a small chip area can be achieved by linear arrays in conjunction with compact memory blocks based on three-transistor cells.<>