Process optimization of high performance ion implanted GaAs JFETs

The strategy, implementation, and results of the optimization of an all-ion-implanted, 0.6- mu m GaAs junction field effect transistor (JFET) process for high-speed, low-power, direct coupled FET logic (DCFL) digital ICs are described. The process has been optimized to provide maximum device performance while concurrently minimizing short channel effects for optimal manufacturability. 15-keV ion implantation is used to form a shallow p-gate (<650 AA) for minimal sidewall capacitance. E-mode threshold voltage variation for gate lengths from 1.2 to 0.5 mu m has been reduced to less than 100 mV. This has allowed excellent across-wafer uniformities averaging 25 mV on 100-mm substrates. Initial test circuit evaluations have demonstrated unity fan-out propagation delays as low as 40 ps and more typically averaging 50 ps. Propagation delays increase about 50% at a fan out of four. The measured noise margins are typically greater than 0.4 V, almost twice that of MESFET DCFL.<>