Experience with biased random pattern generation to meet the demand for a high quality BIST

Three different approaches for LFSR based biased random pattern generation are presented. They can be mapped into custom-made finite state machines satisfying the requirements for BIST. The first approach chooses patterns with constant weights for all PIs/SRLs. The second one uses weights for clusters of inputs. Weights determined from design analysis are applied by a 'rotation' algorithm to cover the highest number of possible faults with simple ring shifters. As a result of these two heuristics, the fault coverage is improved up to 2%. Both approaches require <1% hardware overhead. This was demonstrated for two CMOS VLSI chips. The third approach uses a weight merging algorithm, in which an optimal weight set is determined by merging previously calculated optimal weights for the random pattern resistant faults. This leads to a fault coverage of approximately 99% with an acceptable amount of hardware as is demonstrated for one VLSI chip.<>