Fast test pattern generation for all path delay faults considering various test classes

Theoretical ideas as well as extensive experimental results are presented. The authors begin with an overview of robust and non-robust tests for path delay faults. In particular, they elaborate on five well defined test classes and on their properties. For each class they propose the logic system that is best suited for automatic test pattern generation (ATPG). They then introduce an efficient test pattern generator that is based on a branch-and-bound algorithm. It uses several new multi-valued logic systems, depending on the test class and on the scan design. The results on ATPG for all existing path delay faults in all ISCAS 1989 circuits are presented. A comparison with other ATPG systems reveals that presented algorithm is much faster than existing branch-and-bound algorithms and as fast as techniques based on reduced ordered binary decision diagrams.<>