A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's

A battery-operated 16-Mb CMOS DRAM with address multiplexing has been developed by using an existing 0.5- mu m CMOS technology. It can access data in 36 ns when powered from a 1.8-V battery-source, and 20 ns at 3.3 V. However, this device requires a mere 57 mA of operating current for an 80-ns cycle time and only 5 mu A of standby current at 3.3 V. To achieve both high-speed and low-power operation, the following four circuit techniques have been developed: 1) a parallel column access redundancy (PCAR) scheme coupled with a current sensing address comparator (CSAC), 2) an N&PMOS cross-coupled read-bus-amplifier (NPCA), 3) a gate isolated sense amplifier (GISA) with low V/sub T/, and 4) a layout that minimizes the length of the signal path by employing the lead on chip (LOC) assembly technique.<>