A decision feedback equalizer with a frequency offset compensating circuit for digital cellular radio

The performance of a decision feedback equalizer (DFE) with a frequency offset compensating circuit for the North American digital cellular system (NADC) is presented. The carrier frequency offset at the equalizer's output deteriorates performance of the DFF. Using the unit upper triangular matrix diagonal matrix decomposition type recursive least squares algorithm as an adaptive algorithm, a frequency offset compensating circuit, which is composed of a phase locked loop (PLL), is used. Simultaneous control of the DFE and PLL is effectively utilized to improve the performance. A BER below 3% for all delays up to one symbol period can be achieved when the average E/sub b//N/sub 0/ is 20 dB, the fading frequency is 80 Hz and the carrier frequency offset is 200 Hz in the simulation results. The authors assume the two rays equal power multipath Rayleigh fading model, the same as the NADC specifications. The influence of quantization in the calculation is described. The mantissa-field occupies 8 bits and the exponent-field occupies 6 bits.<>