The Exemplar Logic synthesis system: a logic synthesis tool for field programmable gate arrays

High density programmable logic devices require dedicated synthesis algorithms to maximize the utilization of the device resources. The authors discuss the impact of device architectures on logic synthesis algorithms, and show how device specific optimization allows designers to design for multiple architectures from a common design description. The Exemplar Logic synthesis system combines industry standard design entry methods with architecture specific optimization algorithms. This power lets designers easily migrate PLD, FPGA, or ASIC designs to FPGAs or ASICs, and gives designers using top-down design techniques the flexibility to explore speed versus area tradeoffs between FPGAs and ASICs early in the design cycle.<>